The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the physical design methodology process of integrated systems. In modern electronic circuits, geometries become smaller; clock frequencies increase; and on-chip interconnections gain increased importance in the prediction of performance. Nonetheless, it has been found that from 0.13 μm and below, the layout of an electronic design exhibits profound impacts on device electrical parameters, especially in sub-45 nm nodes. For example, stress effects caused by the length of oxide (LOD) definition or shallow trench isolation (STI) features impact the mobility (μeff), carrier saturation velocity (Vsat), or threshold voltage (Vth) of metal-oxide-semiconductor (MOS) transistors. Well-proximity effect (WPE) also cause significant variation in the threshold voltages depending on the proximity of CMOS (complementary metal-oxide-semiconductor) transistors to an implant well boundary. In addition, a typical design flow often uses various design rules and layout guidelines such as dummy components in module, well creation guidelines, device matching guidelines, etc. to minimize such layout dependent effects by verifying the physical design during sign-off via extraction and re-simulation through multiple iterations. If such verification fails, the design process reverts back to the layout or even back to the schematic design stage and repeats the schematic, layout, and verification process flow iteratively in order to meet a final layout with acceptable performance or manufacturing criteria.
Thus, there exists a need for implementing multi-scenario physically-aware design of an electronic circuit design that captures layout dependent effects among various devices or components early in the design flow such that the impact of such layout-dependent effects may be analyzed during the schematic design stage as well as the physical design stage.